NTLUD3A50PZTAG

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Mfr.Part #
NTLUD3A50PZTAG
Manufacturer
onsemi
Package / Case
6-UDFN Exposed Pad
Datasheet
Download
Description
MOSFET 2P-CH 20V 2.8A UDFN
Stock
7,359
In Stock :
7,359

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Manufacturer :
onsemi
Product Category :
Transistors - FETs, MOSFETs - Arrays
Gate Charge (Qg) (Max) @ Vgs :
10.4nC @ 4.5V
RoHS Status :
ROHS3 Compliant
Number of Pins :
6
Operating Temperature :
-55°C~150°C TJ
Package / Case :
6-UDFN Exposed Pad
FET Feature :
Logic Level Gate
Rds On (Max) @ Id, Vgs :
50m Ω @ 4A, 4.5V
Drain Current-Max (Abs) (ID) :
4.4A
Factory Lead Time :
8 Weeks
Gate to Source Voltage (Vgs) :
8V
Published :
2014
Length :
2mm
Number of Elements :
2
Packaging :
Tape and Reel (TR)
JESD-609 Code :
e3
Lifecycle Status :
ACTIVE (Last Updated: 6 days ago)
Drain to Source Voltage (Vdss) :
20V
Continuous Drain Current (ID) :
2.8A
Height :
500μm
Moisture Sensitivity Level (MSL) :
1 (Unlimited)
Vgs(th) (Max) @ Id :
1V @ 250μA
Element Configuration :
Dual
FET Technology :
METAL-OXIDE SEMICONDUCTOR
ECCN Code :
EAR99
Pbfree Code :
yes
Mounting Type :
Surface Mount
Max Power Dissipation :
500mW
FET Type :
2 P-Channel (Dual)
Pin Count :
6
Input Capacitance (Ciss) (Max) @ Vds :
920pF @ 15V
Surface Mount :
yes
Power Dissipation :
1.4W
Width :
2mm
Turn On Delay Time :
7 ns
Turn-Off Delay Time :
39 ns
Lead Free :
Lead Free
Terminal Finish :
Tin (Sn)
Datasheets
NTLUD3A50PZTAG
Introducing Transistors - FETs, MOSFETs - Arrays onsemi NTLUD3A50PZTAG from Chip IC,where excellence meets affordability. This product stands out with its Number of Pins:6, Operating Temperature:-55°C~150°C TJ, Package / Case:6-UDFN Exposed Pad, Mounting Type:Surface Mount, NTLUD3A50PZTAG pinout, NTLUD3A50PZTAG datasheet PDF, NTLUD3A50PZTAG amp .Beyond Transistors - FETs, MOSFETs - Arrays onsemi NTLUD3A50PZTAG ,we also offer SSM6N57NU,LF, DMN2004DMK-7, AO4629, Our vast inventory has you covered. Contact us now for immediate solutions.

onsemi NTLUD3A50PZTAG


NTLUD3A50PZTAG datasheet pdf and Transistors - FETs, MOSFETs - Arrays product details from ON Semiconductor stock available at

NTLUD3A50PZTAG   Description


  These dual P-channel logic level enhanced mode field effect transistors are produced using on Semiconductor's proprietary high cell density DMOS technology. This very high-density process is specially tailored to minimize state resistance. The device is specially designed for low-voltage applications as a substitute for bipolar digital transistors and small-signal MOSFET.


NTLUD3A50PZTAG      Features


? UDFN Package with Exposed Drain Pads for Excellent Thermal

Conduction

? Low RDS(on)

? Low Profile UDFN 2.0x2.0x0.55 mm for Board Space Saving

? These Devices are Pb?Free, Halogen Free/BFR Free and are RoHS

Compliant


NTLUD3A50PZTAG      Applications


? High Side Load Switch

? Reverse Current Protection

? Battery Switch

? Optimized for Power Management Applications for Portable

Products, such as Cell Phones, PMP, DSC, GPS, and others



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