P2020NXE2MHC
- Mfr.Part #
- P2020NXE2MHC
- Manufacturer
- NXP Semiconductors
- Package / Case
- 689-BBGA Exposed Pad
- Datasheet
- Download
- Description
- IC MPU Q OR IQ 1.2GHZ 689TEBGA
- Stock
- 600
- In Stock :
- 600
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- Manufacturer :
- NXP Semiconductors
- Product Category :
- Microprocessors
- JESD-30 Code :
- S-PBGA-B689
- RoHS Status :
- ROHS3 Compliant
- Supply Voltage :
- 1.05V
- Moisture Sensitivity Level (MSL) :
- 3 (168 Hours)
- HTS Code :
- 8542.31.00.01
- Core Processor :
- PowerPC e500v2
- Factory Lead Time :
- 12 Weeks
- Number of Terminations :
- 689
- Security Features :
- Cryptography, Random Number Generator
- Bit Size :
- 32
- Number of Cores/Bus Width :
- 2 Core 32-Bit
- JESD-609 Code :
- e2
- Height Seated (Max) :
- 2.46mm
- Packaging :
- Tray
- Co-Processors/DSP :
- Security; SEC 3.3
- Length :
- 31mm
- Additional Interfaces :
- CAN, I2C, IrDA, LIN, SCI, SDHC, SPI, UART/USART
- Terminal Position :
- BOTTOM
- Terminal Form :
- Ball
- Ethernet :
- 10/100/1000Mbps (3)
- Terminal Finish :
- TIN COPPER/TIN SILVER
- Integrated Cache :
- yes
- Operating Temperature :
- -40°C~125°C TA
- Series :
- QorIQ P2
- uPs/uCs/Peripheral ICs Type :
- MICROPROCESSOR
- ECCN Code :
- 5A002.A.1
- USB :
- USB 2.0 + PHY (2)
- Power Supplies :
- 1.05V
- RAM Controllers :
- DDR2, DDR3
- Time@Peak Reflow Temperature-Max (s) :
- 40
- Terminal Pitch :
- 1mm
- Surface Mount :
- yes
- Published :
- 2002
- Speed :
- 1.2GHz
- Boundary Scan :
- yes
- Graphics Acceleration :
- No
- Peak Reflow Temperature (Cel) :
- 260
- Base Part Number :
- P2020
- Package / Case :
- 689-BBGA Exposed Pad
- Format :
- Floating Point
- Datasheets
- P2020NXE2MHC

1mm PowerPC e500v2 1.05V 32-bit Microprocessor QorIQ P2 Series P2020 1.05V 689-BBGA Exposed Pad
P2020NXE2MHC Description
A link status bit (TBI SR [Link Status]) in the TBI Status Register (SR) represents the current state of the SGMII link. The TBI link status bit should become a b'1 after detecting IDLE sequences if Auto-Negotiation (AN) is disabled, and stay at b'1 as long as valid data is received and the TBI is not reset. After numerous invalid characters are received or the TBI is reset, the TBI link status bit should become a b'0, indicating the link is down. When AN is enabled, the TBI link status bit is not set to b'1 until auto-negotiation is complete (TBI CR [AN DONE]=1), but the same criteria apply as when AN is disabled for the TBI link status bit to be set to b'1.
P2020NXE2MHC Features
? PIC (programmable interrupt controller) that adheres to the OpenPIC standard
? Two DMA controllers with four channels
? Timers, DUART, and two I2C controllers
? A more powerful local bus controller (TBC)
? 16 I/O signals for generic use
? Temperature of the operating junction
? WB-TePBGA II, 689-pin, 31 x 31 mm (wire bond temperature-enhanced plastic BGA)
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