NLV14013BCPG

Manufacturer :

onsemi

Product Category :

Flip Flops

Standard Package Name :

DIP

Package Length :

19.69(Max)

Lead Shape :

Through Hole

Reach Compliance Code :

Unknown

Package Shape :

RECTANGULAR

Terminal Finish :

Tin (Sn)

Mounting :

Through Hole

Supply Voltage-Min (Vsup) :

3 V

Maximum Propagation Delay Time @ Maximum CL (ns) :

150@10V|100@15V|350@5V

Propagation Delay (tpd) :

350 ns

Number of Elements per Chip :

2

Maximum Low Level Output Current (mA) :

4.2(Min)

Temperature Grade :

Military

Terminal Pitch :

2.54 mm

Number of Element Inputs :

1

Input Signal Type :

SINGLE-ENDED

PCB changed :

14

Logic Family :

4000

Terminal Position :

Dual

Bus Hold :

No

Number of Element Outputs :

1

Minimum Operating Temperature (°C) :

-55

Triggering Type :

Positive-Edge

Typical Operating Supply Voltage (V) :

3.3|9|12|15|5

Set/Reset :

Set/Reset

Seated Height-Max :

4.69 mm

Number of Bits :

1

HTS Code :

8542.39.00.01

Series :

*

Maximum High Level Output Current (mA) :

-4.2(Min)

Polarity :

Inverting/Non-Inverting

Process Technology :

CMOS

Length :

18.86 mm

Package :

Bulk

Terminal Form :

THROUGH-HOLE

Maximum Operating Supply Voltage (V) :

18

Factory Lead Time :

1 Week

Number of Channels per Chip :

2

Supply Voltage-Max (Vsup) :

18 V

Packaging :

Tube

Manufacturer :

ON Semiconductor

Screening Level :

AEC-Q100

Package Width :

7.11(Max)

ECCN (US) :

EAR99

Trigger Type :

POSITIVE EDGE

Output Polarity :

Complementary

Peak Reflow Temperature (Cel) :

NOT SPECIFIED

Package Height :

4.95(Max)

Maximum Quiescent Current (mA) :

0.004

Number of Functions :

2

JESD-30 Code :

R-PDIP-T14

Family :

4000/14000/40000

Pin Count :

14

Surface Mount :

No

Logic IC Type :

D FLIP-FLOP

Absolute Propagation Delay Time (ns) :

450

Maximum Operating Temperature (°C) :

125

Minimum Operating Supply Voltage (V) :

3

Number of Terminals :

14

Width :

7.62 mm

Logic Function :

D-Type

Product Status :

Active

RoHS Status :

RoHS Compliant

Supplier Package :

PDIP

Technology :

CMOS

Propagation Delay Test Condition (pF) :

50

JESD-609 Code :

e3