STPCC5HEBC
- Mfr.Part #
- STPCC5HEBC
- Manufacturer
- STMicroelectronics
- Package / Case
- 388-BGA
- Datasheet
- Download
- Description
- IC SYSTEM-ON-CHIP X86 388BGA
- Stock
- 66
- In Stock :
- 66
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- Manufacturer :
- STMicroelectronics
- Product Category :
- Application Specific Microcontrollers
- Operating Supply Voltage :
- 2.5V
- Data Bus Width :
- 64B
- Supply Voltage :
- 2.5V
- Time@Peak Reflow Temperature-Max (s) :
- NOT SPECIFIED
- Voltage - Supply :
- 2.45V~3.6V
- Terminal Position :
- BOTTOM
- Number of Pins :
- 388
- Core Processor :
- X86
- HTS Code :
- 8542.39.00.01
- Bus Compatibility :
- PCI; ISA
- Mount :
- Surface Mount
- Memory Type :
- External Program Memory
- Length :
- 35mm
- Terminal Finish :
- Tin/Lead (Sn/Pb)
- Package / Case :
- 388-BGA
- Operating Temperature :
- 0°C~85°C
- Base Part Number :
- STPCC5
- Terminal Form :
- Ball
- Power Supplies :
- 3.3V
- Mounting Type :
- Surface Mount
- Moisture Sensitivity Level (MSL) :
- 3 (168 Hours)
- Boundary Scan :
- yes
- Pin Count :
- 388
- RAM Size :
- External
- RoHS Status :
- ROHS3 Compliant
- uPs/uCs/Peripheral ICs Type :
- MULTIFUNCTION PERIPHERAL
- Number of Terminations :
- 388
- Address Bus Width :
- 32
- Controller Series :
- STPC® Consumer-II
- Max Frequency :
- 133MHz
- Height Seated (Max) :
- 2.38mm
- JESD-609 Code :
- e0
- Peak Reflow Temperature (Cel) :
- NOT SPECIFIED
- Interface :
- EBI/EMI, I2C, IDE, ISA, Local Bus
- Qualification Status :
- Not Qualified
- Applications :
- Set-Top Boxes, TV
- Program Memory Type :
- External Program Memory
- Terminal Pitch :
- 1.27mm
- Packaging :
- Tray
- Datasheets
- STPCC5HEBC
2.5V V 2.38mm mm Interface - UARTs (Universal Asynchronous Receiver Transmitter) 35mm mm 388 NOT SPECIFIED 388
STPCC5HEBC Description
The STPC Consumer-II integrates a standard 5thgeneration x86 core, a Synchronous SDRAM controller, a graphics subsystem, a video pipeline, and support logic including PCI, ISA, and IDEcontrollers to provide a single consumer-orientated PC compatible subsystem on a single device. The device is based on a tightly coupled UnifiedMemory Architecture (UMA), sharing memory between the CPU, the graphics and the video.
STPCC5HEBC Features
POWERFUL x86 PROCESSOR
64-BIT SDRAM UMA CONTROLLER
VGA & SVGA CRT CONTROLLER
135 MHz RAMDAC
2D GRAPHICS ENGINE
VIDEO INPUT PORT
VIDEO PIPELINE
- UP-SCALER
- VIDEO COLOUR SPACE CONVERTER
- CHROMA & COLOUR KEY SUPPORT
TV OUTPUT
- THREE-LINE FLICKER FILTER
ITU-R 601/656 SCAN CONVERTER
- NTSC / PAL COMPOSITE, RGB, S-VIDEO
PCI MASTER/ SL _AVE / ARBITER
ISA MASTER 1 SL _AVE
OPTIONAL 16-BIT LOCAL BUS INTERFACE
EIDE CONTROLLER
IFC INTERFACE
IPC
- DMA CONTROLLER
- INTERRUPT CONTROLLER
- TIMER / COUNTERS
POWER MANAGEMENT UNIT
JTAG IEEE1149.1
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