74LV27D,118

Manufacturer :

NXP Semiconductors

Product Category :

Gates and Inverters

Number of Inputs :

3

Terminal Finish :

NICKEL PALLADIUM GOLD

Schmitt Trigger :

No

Logic Type :

NOR Gate

Current - Output High, Low :

12mA 12mA

Moisture Sensitivity Level (MSL) :

1 (Unlimited)

Family :

LV/LV-A/LVX/H

Height Seated (Max) :

1.75mm

Load Capacitance :

50pF

Logic Level - Low :

0.3V ~ 0.8V

JESD-609 Code :

e4

Operating Temperature :

-40°C~125°C

JESD-30 Code :

R-PDSO-G14

Logic Level - High :

0.9V ~ 2V

Current - Quiescent (Max) :

40μA

Packing Method :

Tape and Reel

Voltage - Supply :

1V~5.5V

Prop. Delay@Nom-Sup :

16 ns

Series :

74LV

Published :

2003

RoHS Status :

ROHS3 Compliant

Terminal Position :

Dual

Number of Functions :

3

Qualification Status :

Not Qualified

Pin Count :

14

Peak Reflow Temperature (Cel) :

260

Mounting Type :

Surface Mount

Terminal Pitch :

1.27mm

Max I(ol) :

0.016 A

Packaging :

Tape and Reel (TR)

Surface Mount :

yes

Package / Case :

14-SOIC (0.154, 3.90mm Width)

Supply Voltage-Min (Vsup) :

1V

Supply Voltage :

3.3V

Base Part Number :

74LV27

Propagation Delay (tpd) :

27 ns

Number of Terminations :

14

Terminal Form :

Gull wing

Supply Voltage-Max (Vsup) :

5.5V

Number of Circuits :

3

Length :

8.65mm

Time@Peak Reflow Temperature-Max (s) :

30

Max Propagation Delay @ V, Max CL :

10ns @ 3.3V, 50pF