74LV27D,112

Manufacturer :

NXP Semiconductors

Product Category :

Gates and Inverters

JESD-609 Code :

e4

Schmitt Trigger :

No

Supply Voltage-Min (Vsup) :

1V

Supply Voltage :

3.3V

JESD-30 Code :

R-PDSO-G14

Terminal Position :

Dual

Packaging :

Tube

Supply Voltage-Max (Vsup) :

5.5V

Current - Output High, Low :

12mA 12mA

Prop. Delay@Nom-Sup :

16 ns

Mounting Type :

Surface Mount

Moisture Sensitivity Level (MSL) :

1 (Unlimited)

Number of Circuits :

3

Base Part Number :

74LV27

Propagation Delay (tpd) :

27 ns

Peak Reflow Temperature (Cel) :

260

Terminal Finish :

Nickel/Palladium/Gold (Ni/Pd/Au)

Package / Case :

14-SOIC (0.154, 3.90mm Width)

Logic Type :

NOR Gate

Series :

74LV

Family :

LV/LV-A/LVX/H

Surface Mount :

yes

RoHS Status :

ROHS3 Compliant

Max I(ol) :

0.016 A

Logic Level - Low :

0.3V ~ 0.8V

Qualification Status :

Not Qualified

Max Propagation Delay @ V, Max CL :

10ns @ 3.3V, 50pF

Length :

8.65mm

Terminal Form :

Gull wing

Load Capacitance :

50pF

Published :

2003

Pin Count :

14

Current - Quiescent (Max) :

40μA

Operating Temperature :

-40°C~125°C

Number of Functions :

3

Number of Inputs :

3

Voltage - Supply :

1V~5.5V

Logic Level - High :

0.9V ~ 2V

Number of Terminations :

14

Time@Peak Reflow Temperature-Max (s) :

30

Height Seated (Max) :

1.75mm

Terminal Pitch :

1.27mm